The leaky semicolon: compositional semantic dependencies for relaxed-memory concurrency

Program logics and semantics tell a pleasant story about sequential composition: when executing (S1;S2), we first execute S1 then S2. To improve performance, however, processors instructions out of order, compilers reorder programs even more dramatically. By design, single-threaded systems cannot observe these reorderings; multiple-threaded can, making the considerably less pleasant. A formal attempt to understand resulting mess is known as “relaxed memory model.” Prior models either fail address composition directly, or overly restrict compilers, permit nonsense thin-air behaviors which are unobservable in practice. support while targeting modern hardware, enrich standard event-based approach with preconditions families predicate transformers. When calculating meaning (S1; S2), transformer applied precondition an event e from S2 chosen based on set events upon depends. We apply this two existing models.